Method and apparatus for stack manipulation in a pipelined proce

Details Method and apparatus for stack manipulation in a pipelined proce Method and apparatus for stack manipulation in a pipelined proce

1994-09-14

1996-05-28

Lall, Parshotam S.

Boots, shoes, and leggings

395400, 3642477, 3642545, 3642318, 364DIG1, 3649576, 36496426, G06F 1202, G06F 935

Patent

active

055220517

ABSTRACT:
A method and apparatus for accessing and manipulating a stack register file during an instruction execution through a pipelined execution unit. A plurality of control directives are provided to the apparatus. A stack register file having a plurality of physical registers is provided for storing data. The physical register file has a stack organization. A pointer table register file having a plurality of pointer table registers stores physical register addresses. A TAG register file comprising a plurality of TAG registers, one for each of the pointer table register, is provided for signalling whether the associated physical register is empty or full. A TOS address generator generates an address of one of the pointer table registers which contains an address of one of the physical registers which is the current top of stack register. A pointer table address generator generates for each of the instruction operands, an address of one of the pointer table registers which contains the address of one of the physical registers which contains the operand. A TAG checking and setting generator reads the TAG register file and writes into the TAG register file.

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patent: 5201056 (1993-04-01), Daniel et al.
patent: 5367650 (1994-11-01), Sharangpani
Yoshida, T. et al. A strategy for avoiding pipeline interlock delays in a microprocessor IEEE Computer Soc Press, Los Alamitor, CA 17-19 Sep. 1990.

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