Multiprocessor system with shared cache and data input/output ci

Details Multiprocessor system with shared cache and data input/output ci Multiprocessor system with shared cache and data input/output ci

1993-08-02

1996-12-03

Kim, Matthew M.

395454, 395457, 395455, 395448, 395445, 395447, 395855, G06F 1208

Patent

active

055817343

ABSTRACT:
A high performance shared cache is provided to support multiprocessor systems and allow maximum parallelism in accessing the cache by the processors, servicing one processor request in each machine cycle, reducing system response time and increasing system throughput. The shared cache of the present invention uses the additional performance optimization techniques of pipelining cache operations (loads and stores) and burst-mode data accesses. By including built-in pipeline stages, the cache is enabled to service one request every machine cycle from any processing element. This contributes to reduction in the system response time as well as the throughput. With regard to the burst-mode data accesses, the widest possible data out of the cache can be stored to, and retrieved from, the cache by one cache access operation. One portion of the data is held in logic in the cache (on the chip), while another portion (corresponding to the system bus width) gets transferred to the requesting element (processor or memory) in one cycle. The held portion of the data can then be transferred in the following machine cycle.

REFERENCES:
patent: 4056845 (1977-11-01), Churchill, Jr.
patent: 4195342 (1980-03-01), Joyce et al.
patent: 4371929 (1983-02-01), Brann et al.
patent: 4374410 (1983-02-01), Sakai et al.
patent: 4442487 (1984-04-01), Fletcher et al.
patent: 4445174 (1984-04-01), Fletcher
patent: 4527238 (1985-07-01), Ryan et al.
patent: 4695943 (1987-09-01), Keeley et al.
patent: 4736293 (1988-04-01), Patrick
patent: 4783736 (1988-11-01), Ziegler et al.
patent: 4905141 (1990-02-01), Brenza
patent: 4941088 (1990-07-01), Shaffer et al.
patent: 4953073 (1990-08-01), Moussouris et al.
patent: 4959777 (1990-09-01), Holman, Jr.
patent: 5070444 (1991-12-01), Kubo et al.
patent: 5185878 (1993-02-01), Baror et al.
patent: 5386537 (1995-01-01), Asano
patent: 5398325 (1995-03-01), Chang et al.
Wright, RISC boards target real-time applications, EDN, v34, n7, p. 69(8), Mar. 30, 1989.
Gilmour, Speed the execution of your MuP-MuC software, EDN, v34, n11, p. 177 (8), May 25, 1989.
Atkins, Dual processors boost computer power, Electronics Design, v40, n4, p. 122(6), Feb. 20, 1992.
Andrews, The Pentium gets GaAs, Computer Design, v32, n7, p33 (3), Jul. 1993.
IBM TDB, "Improved Store-Thru Cache", vol. 34, No. 1, Jun. 1991, pp. 370-374.

Affiliated with

Also associated with

Rating

Multiprocessor system with shared cache and data input/output ci does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiprocessor system with shared cache and data input/output ci, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiprocessor system with shared cache and data input/output ci will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-794542