Fault control system for communications buses in multi-processor

Details Fault control system for communications buses in multi-processor Fault control system for communications buses in multi-processor

1995-04-06

1996-05-28

Canney, Vincent P.

39518211, 39520021, G06F 1110

Patent

active

055220304

ABSTRACT:
A fault control system for a multi-processor system in which a plurality of processors are connected to each other via first and second communications buses, including a plurality of stations provided in the first communications bus and respectively connected to the processors. A supervisory station function unit, which is provided in each of the stations, supervises a state of the first communications bus. An ordinary station function unit, which is provided in each of the stations, establishes an interface between the processors and the first communications bus. One of the stations functions as a supervisory station in which only the supervisory station function unit is activated, and remaining stations respectively function as ordinary stations in which only the respective ordinary station function units are activated. A control unit, which is provide in one of the processors, activates the supervisory stations function unit provided in one of the remaining stations, and disables the supervisory station function unit provided in the supervisory station when a fault has occurred in the supervisory station.

REFERENCES:
patent: 5202980 (1993-04-01), Morita et al.
patent: 5307481 (1994-04-01), Shimazaki et al.
Computer Architecture and Organization Second Edition by John P. Hayes .COPYRGT.1988 by McGraw-Hill Inc. pp. 664-670.
An Introduction to Operating Systems Second Edition by Harvey M. Deitel, .COPYRGT.1990 by Addison-Wesley Publishing Co. p. 536.
Operating Systems Concepts Third Edition by Abraham Silberschatz .COPYRGT.1991 by Addison-Wesley Publishing Co. pp. 438, 439.

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