Manufacturing method of thin film transistor

Fishing – trapping – and vermin destroying

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437101, 437233, 257 66, 257 72, H01L 2904, H01L 29784

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053189191

ABSTRACT:
A manufacturing method of a thin film transistor, wherein a laminated body consisting of an intrinsic amorphous silicon layer and a conductive amorphous silicon layer is formed on a glass substrate, and annealed at low temperatures not higher than 600.degree. C. thereby obtaining a polycrystalline silicon film. The conductive amorphous silicon layer gives girth to a core for polycrystallization, and therefore the intrinsic amorphous silicon layer is easily recrystallized by annealing at low temperatures.

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patent: 5102813 (1992-04-01), Kobayashi et al.
Low Temperature Polysilicon TET with Two-Layer Gate Insulator Using Photo-GVD and APCVD SiO.sub.2, IEEE Electron Device Letters vol. 9, No. 6, Jun. 1988.
Japan J. Appl. Phys. vol. 21, No. 6, Jun., 1982, pp. L381-L383.

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