Method of fabricating a flash memory cell

Details Method of fabricating a flash memory cell Method of fabricating a flash memory cell

1993-07-22

1994-03-29

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 52, 437238, H01L 21265

Patent

active

052984478

ABSTRACT:
A flash memory cell includes the usual thermal oxide layer deposited above the substrate including the source and the drain. On the thermal oxide layer, a silicon rich oxide layer is formed. Above the silicon rich oxide layer a gate structure is formed of layer of polysilicon separated by an intermediate dielectric layer. The lower polysilicon layer commences as an initial portion of the layer of small grain size followed by either amorphous or large grain size material.

REFERENCES:
patent: 4804637 (1989-02-01), Smayling et al.
patent: 4833096 (1989-05-01), Huang et al.
patent: 5019527 (1991-05-01), Ohshima et al.
"Electrically-Alterable Memory Using A Dual Electron Injector Structure" by D. J. Dimaria et al., Elec. Dev. Let. vol. EDL-1, No. 9, Sep. 1990.
"Optimized Silicon-Rich(SRO) Deposition Process for 5V Only Flash EEPROM Applications" by L. Dori et al., IEEE Electron Device Letters, Jun. 1993, vol. 14, No. 6, pp. 283-285.

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