Analog multiplier using an octotail cell or a quadritail cell

Details Analog multiplier using an octotail cell or a quadritail cell Analog multiplier using an octotail cell or a quadritail cell

1993-12-21

1996-12-03

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

327357, 327359, 327105, 327113, 327119, 455333, H03K 522

Patent

active

055812104

ABSTRACT:
A multiplier in which simplification of a circuit configuration and reduction of a current consumption can be realized. There are provided with first, second, third and fourth pairs of transistors whose capacities are the same with each other and these four pairs are driven by a constant current source, respectively. A sum of first and second input voltage is applied in positive phase to an input end of the first pair and the sum is applied in opposite phase to the other input end thereof. A difference of the first and second input voltages is applied in positive phase to an input end of the second pair and the difference is applied in opposite phase to the other input end thereof. Input ends of the third pair and those of the fourth pair are coupled together to be applied with a direct current voltage. The output ends coupled of the first pair and those coupled of the third pair are coupled together to form one of differential output ends, and the output ends coupled of the second pair and those coupled of the fourth pair are coupled together to form the other of the differential output ends.

REFERENCES:
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patent: 4546275 (1985-10-01), Pena-Finol et al.
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patent: 5107150 (1992-04-01), Kimura
patent: 5118945 (1992-06-01), Winschuh et al.
patent: 5313063 (1994-05-01), Netzer
patent: 5353534 (1994-10-01), Kimura
K. Kimura, "A Unified Analysis of Four-Quadrant Analog Multipliers Consisting of Emitter and . . . on Low Supply Voltage", IEICE Transactions on Electronics, vol. E76-C, No. 5, May 1993, pp. 714-737.
Klaas Bult, "Analog CMOS Suare-Law Circuits".

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