Method of making capacitor for stack dram cell

Details Method of making capacitor for stack dram cell Method of making capacitor for stack dram cell

1994-10-05

1996-05-28

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 218242

Patent

active

055211127

ABSTRACT:
A method, and resultant structure, for fabricating a DRAM (Dynamic Random Access Memory) cell with a stack capacitor is described. AMOS (metal oxide semiconductor) device and adjacent word line are provided, having first and second active regions, in a silicon substrate. A first insulating layer is formed over the MOS device and word line, and patterned to form a cell contact opening to the first active region. A first conductive layer is formed over the first insulating layer and in the opening. A second insulating layer is formed over the first conductive layer, and patterned to form a second opening centered over the cell contact opening. Silicon nitride spacers are formed on the vertical surfaces of the second opening. The first conductive layer is oxidized within the second opening, forming an oxide mask. The silicon nitride spacers are removed. A third opening is formed in the first conductive layer, in areas not masked by the oxide mask. The oxide mask and the second insulating layer are removed. A photoresist mask is formed between, over, and adjacent to the third opening. The first conductive layer is patterned in areas not masked by the photoresist mask, thereby forming a bottom electrode for the stack capacitor. The capacitor is completed by forming a capacitor dielectric and top electrode.

REFERENCES:
patent: 5438013 (1995-08-01), Kim et al.
patent: 5444005 (1995-08-01), Kim et al.

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