Method and apparatus for providing bus parity

Details Method and apparatus for providing bus parity Method and apparatus for providing bus parity

1990-06-14

1992-08-04

Smith, Jerry

Excavating

371 295, 371 492, G06F 1100

Patent

active

051365944

ABSTRACT:
A method for checking parity on, for example, an Extended Industry Standard Architecture (EISA) bus. In a 32-bit information bus, four parity pins may be provided. During a first clock cycle the pins are all driven high and during a second clock cycle the pins are all driven low. This characteristic pattern is detected by a slave device and provides an indication that parity data will be transmitted on the four parity pins. After an indication of parity support the pins are provided with parity bits for error detection.

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