Method for fabricating true LDD devices in a MOS technology

Details Method for fabricating true LDD devices in a MOS technology Method for fabricating true LDD devices in a MOS technology

1994-12-15

1996-12-03

Quach, T. N.

Fishing, trapping, and vermin destroying

437 44, 437 57, H01L 21336

Patent

active

055808042

ABSTRACT:
A method of fabricating a true-LDD MOS transistor is described. The fabrication method includes the step of forming an LDD photoresist mask layer on a semiconductor substrate. The mask is aligned to the gate structure and extended to cover a source region, a lightly doped ion implant is performed in the drain region which is self-aligned with the gate structure and the LDD photoresist mask is removed. Spacers are then formed on the source side and the drain side of the gate structure and a heavily doped ion implant is applied to dope the source region and the drain region which are self-aligned with the gate structure and spacers.

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Buti, T., et al., "Asymmetric Halo Source GOLD Drain (HS-GOLD) Deep Sub-half Micron n-MOSFET Design for Reliability and Performance", International Electron Devices Meeting (IEDM) Technical Digest, Jul. 1989, pp. 617-620.
Horiuchi, T., et al., "An Asymmetric Sidewall Process for High Performance LDD MOSFET's", IEEE Transactions on Electron Devices, vol. 41, No. 2, pp. 186-189, Feb. 1994.

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