Fishing – trapping – and vermin destroying
Patent
1995-04-13
1996-12-03
Nguyen, Tuan H.
Fishing, trapping, and vermin destroying
437 41, 437 43, 437 26, 437 62, 437974, 148DIG135, 148DIG12, H01L 21265
Patent
active
055808026
ABSTRACT:
A silicon-on-insulator (SOI) gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) includes a source, channel and drain surrounded by a top gate and a buried bottom gate, the latter of which also has application for other buried structures and is formed on a bottom gate dielectric which was formed on source, channel and drain semiconductor layer of an SOI wafer. After forming a planar bottom insulator layer on the bottom gate and bottom gate dielectric, the SOI wafer is flip-bonded onto an oxide layer of a bulk silicon wafer, thereby encapsulating the buried bottom gate electrode in insulating oxide, after which the SOI substrate and the etch-stop SOI oxide layer are removed to expose the SOI semiconductor layer which is processed to form the source, drain and channel in a mesa structure on which is deposited a top gate dielectric, a top gate, and top gate insulator as well as four conductors for connecting to the source, drain, top gate and bottom gate. The latter two electrodes can be independently controlled or commonly controlled for enhanced operation of GAA MOSFET having improved isolation and reduced parasitic capacitance due to the use of encapsulating insulation layers of the merged wafer consisting of the bonded SOI wafer and bulk silicon wafer.
REFERENCES:
patent: 4771016 (1988-09-01), Bajor et al.
patent: 4902641 (1990-02-01), Koury, Jr.
patent: 5034343 (1991-07-01), Rouse et al.
patent: 5168078 (1992-12-01), Reisman et al.
patent: 5468674 (1995-11-01), Walker et al.
Modes of Operation and Radiation Sensitivity of Ultrathin SOI Transistors Mayer, D. C., IEEE Trans. Electron Devices, vol. 37, No. 5, May 1990, pp. 1280-1288.
A Fully Depleted lean-Channel Transistor (DELTA)--A Novel Vertical Ultra Thin SOI MOSFET Hisamoto, D., Kaga, T., Kawamoto, T., Takeda, E.--IEDM Tech Digest, 1989, pp. 833-836.
Silicon-On-Insulator Gate-All-Around Device Colinge, J. P., Gao, M. H., Romano-Rodriguez, A., Maes, H., Claeys, C.--IEDM Tech Digest, 1990, pp. 595-598.
Radiation Effects in Gate-All-Around Structures Lawrence, R. K., Colinge, J. P., Hughes, H. L.--1991 IEEE Int'l SOI Conf., pp. 80-81.
C.M.O.S. Devices Fabricated on Buried SiO.sub.2 Layers Formed by Oxygen Implantation Into Silicon Izumi, K., Doken, M., Ariyoshi, H.--Electronics Lett. 14, 1978, p. 593.
Formation of Multiply Faulted Defects in Oxygen Implanted Silicon-On-Insulator Material Visitserngtrakul, S., Krause, S. J.--J. Appl. Phys. 69, Feb. 1991, pp. 1784-1786.
A Field Assisted Bonding Process for Silicon Dielectric Isolation Frye, R. C., Griffith, J. E., Wong, Y. H.--J Electrochem. Soc. 133, Aug. 1986, pp. 1673-1677.
Silicon-On-Insulator by Bonding and Etch-Back Lasky, J. B., Stiffler, S. R., White, F. R., Abernathey, J. F.--IEDM Tech. Digest, 1985, pp. 684-687.
Bonding of Silicon Wafers for Silicon-On-Insulator Maszara, W. P., Goetz, G., Caviglia, A., McKitterick, J. B.--J. Appl. Phys. 64(10), Nov. 1988, pp. 4943-4950.
VLSI SOI Fabrication by SIMOX Wafer Bonding (SWB) Tong, W. Y., Gosele, U.--1992 IEEE Int'l SOI Conf. Proc., 1992, pp. 72-73.
Dual-Gate SOI CMOS Technology by Local Overgrowth (LOG) Zingg, R. P., Hofflinger, B., Neudick., G. W.--1989 IEEE SOS/SOI Tech Conf. Proc., 1989, pp. 134-135.
Dual Gate Opeation and Volume Inversion in n-Channel SOI MOSFETs Venkatesan, S., Neudeck, G. W., Pierret, R. F.--IEEE Electron Device Letts. 13(1), Jan. 1992, pp. 44-46.
MacWilliams Kenneth P.
Mayer Donald C.
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