Digital signal multiplexing apparatus and demultiplexing apparat

Multiplex communications – Wide area network – Packet switching

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

3701101, 3701054, H04J 304

Patent

active

051365871

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention generally relates to digital signal multiplexing apparatuses and demultiplexing apparatuses, and more particularly to a digital signal multiplexing apparatus for byte-multiplexing a high-speed digital signal and for transmitting a multiplexed signal, and a demultiplexing apparatus for demultiplexing the multiplexed signal and for outputting a high-speed digital signal.


BACKGROUND ART

A system is known in which transmission and reception of a high-speed digital signal are made using a synchronous communication network which uses optical fiber cables. In such a synchronous communication network, an oscillator is provided to generate a main clock within the system. This main clock is used in common on the transmitter end and the receiver end. Normally, a plurality of input signals are subjected to a hierarchical multiplexing process a plurality of times and converted into a high-speed multiplexed signal which is transmitted. The input signals are multiplexed in bytes. The signal speed increases every time the multiplexing takes place. For this reason, a circuit which operates at a high speed is necessary to carry out the multiplexing. Heat generated by a circuit which operates at the high speed is large, and the large heat generation makes it difficult to reduce the size of the equipment. Accordingly, in order to minimize the circuit scale, it is necessary to reduce the circuit parts which operate at the high speed and reduce the power consumption.
The SONET (synchronous optical network) is known as a high-speed transmission network using byte multiplexing. As shown in FIG. 1, an STS-1 signal of the SONET system has 8 bits in one byte and forms one frame in 90 bytes.times.9 columns.times.8 bits=6480 bits. One frame is 125 .mu.s, and the bit rate is 51.84 MHz. A frame format of the STS-1 signal shown in FIG. 1 is formed for every channel. 2 bytes at the head of the frame format are frame synchronizing patterns A1 and A2, and next one byte is a channel identification pattern C1. SOH (section overhead), LOH (line overhead) and POH (path overhead) are control data added to the information which is to be transmitted.
The plurality of STS-1 signals having the above described frame format are simply byte-multiplexed (no format conversion is made). FIG. 2 shows the byte multiplexing of 3 STS-1 signals. The STS-1 signals of the 3 S channels #1, #2 and #3 are byte-multiplexed to generate an STS-3 signal of 155.52 MHz. This STS-3 signal is standardized as an STM-1 signal according to the CCITT Recommendations. It is assumed that the STS-1 signals are transmitted as optical signals. The two bytes of frame synchronizing patterns A1 and A2 and one byte of channel identification pattern C1 are added to the head of the data of the three channels #1 through #3, and the STS-3 signal is formed by the byte multiplexing as indicated by dotted arrows. In this case, since insertion of the frame pattern or the like is not made as the STS-3 signal and the byte multiplexing is carried out so that the heads the channels #1 through #3 match, a frame multiplexed synchronizing pattern of the STS-3 signal is formed of six bytes.
In addition, the frame synchronizing patterns A1 and A2 of each of the channels #1 through #3 are the same, and patterns A1="11110110" and A2="00101000" are used. Further, the channel identification pattern C1 is selected to mutually different patterns among the channels #1 through #3.
Returning to FIG. 1, B1 through B3 are byte interleaving parities, C2 is a signal label byte indicating the existence
on-existence of information, D1 through D12 are data communication bytes for transferring status information or the like between equipment, E1 and E2 are order wire bytes, F1 and F2 are user channel bytes, G1 is a path status byte for detecting a parity error of a reception signal and for returning it to a far end equipment, H1 and H2 are pointers having variable slot function for fetching an asynchronous system, H3 is a pointer having variable slot function in stuffing, H4 i

REFERENCES:
patent: 4052566 (1977-10-01), MacKay
patent: 4313193 (1982-01-01), Nakano et al.
patent: 4675861 (1987-06-01), Uttermark
patent: 4744082 (1988-03-01), Fujimura et al.
patent: 4899339 (1990-02-01), Shibagaki et al.
patent: 4920535 (1990-04-01), Watanabe et al.
patent: 4984238 (1991-01-01), Watanabe et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Digital signal multiplexing apparatus and demultiplexing apparat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital signal multiplexing apparatus and demultiplexing apparat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital signal multiplexing apparatus and demultiplexing apparat will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-784861

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.