1990-10-16
1992-02-11
Wojciechowicz, Edward J.
357 234, 357 42, 357 46, 357 48, 357 59, H01L 2702
Patent
active
050879545
ABSTRACT:
In a MOS-type integrated circuit, a source and a gate of a double diffusion MOSFET of an n-channel type and a drain and a gate of a double diffusion MOSFET of a p-channel type are in an island region surrounded by an n-type annular contact region having high impurity concentration. An n epitaxial layer, in each island region, is used for the sources and drains of both MOSFETs. The drain electrode of the p-channel MOSFET is connected to the gate electrode of the n-channel MOSFET. With this structure, the power consumption of the circuit is decreased, and the operating speed thereof is increased.
REFERENCES:
patent: 4403395 (1983-09-01), Curran
patent: 4628341 (1986-12-01), Thomas
patent: 4879584 (1989-11-01), Takagi et al.
patent: 4890146 (1989-12-01), Williams et al.
Kabushiki Kaisha Toshiba
Wojciechowicz Edward J.
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