Input circuit for CCD delay line

Details Input circuit for CCD delay line Input circuit for CCD delay line

1990-08-30

1992-02-11

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307491, 307494, 307359, 328 66, 377 58, 357 24, H03K 513, G06G 712, G11C 1928, H01L 2978

Patent

active

050878433

ABSTRACT:
An input circuit for a charge-coupled device (CCD) delay line is comprised of a semiconductor substrate, a CCD delay line formed on the semiconductor substrate, first and second registers each having substantially the same maximum treating charge amount as that of the CCD delay line and formed on the semiconductor substrate, an input portion of the first register having substantially the same structure as that of the CCD delay line, output portions of the first and second registers having substantially the same structure each other, a control circuit for controlling the second register so that an output signal from the second register becomes a signal corresponding to the maximum treating charge amount, a comparing circuit for comparing output signals of the first and second registers, wherein an output signal of the comparing circuit is fed back to an input source of the input portion of the first register so that the output signal from the first register becomes equal to the output signal from the second register, a voltage of high level of a clock signal is supplied to an input gate of the first register and a voltage of the input source of the first register is supplied to an input source of an input portion of the CCD delay line. Thus, an overflow of charge can be avoided satisfactorily.

REFERENCES:
patent: 4625322 (1986-11-01), Tukazaki et al.

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