Method of manufacturing a bipolar transistor

Details Method of manufacturing a bipolar transistor Method of manufacturing a bipolar transistor

1990-09-13

1991-06-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 28, 437112, 437228, 437978, 357 34, 148DIG43, H01L 21328

Patent

active

050231928

ABSTRACT:
A first device region (20) of one conductivity type is provided adjacent one major surface (11) of a semiconductor body (10). A layer (30) doped with impurities of the opposite conductivity type is provided on the one major surface (11) for forming an extrinsic subsidiary region (41) of a second device region (40) of the opposite conductivity type. An opening (31) is formed through the doped layer (30). Impurities for forming a coupling region (43) of the opposite conductivity type are introduced through the opening (31) prior to defining an insulating first portion (50) on the side wall (32) of the doped layer (30) to form a first window (80). Impurities for forming an intrinsic subsidiary region (42) of the second device region (40) are introduced through the first window (80). A second portion (60) is then defined on the insulating first portion (50) to form a smaller second window (90), and impurities for forming a third device region (70) through the second window (90) so that the extrinsic subsidiary region (41) and third device region are well spaced whilst the coupling region (43) enables good connection between the extrinsic and intrinsic subsidiary regions (41 and 42).

REFERENCES:
patent: 4581319 (1986-04-01), Wieder et al.
patent: 4689872 (1987-09-01), Appels et al.
patent: 4772566 (1988-09-01), Zdebel et al.
patent: 4780427 (1988-10-01), Sakai et al.
Gomi, T. et al.; "A Sub-30 Psec Si Bipolar LSI Technology," IEEE IEDM Tech. Digest, 1988, pp. 744-747.

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