Digital word-serial multiplier circuitry

Details Digital word-serial multiplier circuitry Digital word-serial multiplier circuitry

1989-04-04

1990-11-13

Malzahn, David M.

Boots, shoes, and leggings

G06F 750

Patent

active

049706764

ABSTRACT:
A word serial multiplier includes a first circuit loop for loading a parallel-bit multiplier, and in response to a clock signal sequentially produces a gate signal corresponding to a sequence of bits of the multiplier sample in descending order of significance. A second circuit loop loads a multiplicand sample and in response to the clock signal successively divides the multiplicand sample by the factor two. The more significant bits, exclusive of the least significant bit, of the divided multiplicand sample are coupled to a gating circuit. The gating circuit passes the more significant bits to the input of an accumulator if the corresponding bits of the gate signal exhibit a predetermined state. After a number of cycles of the clock signal, corresponding to the number of bits m of the multiplier sample, the accumulator produces a scaled product equal to the muliplicand times the multiplier times the scale factor of 2.sup.-(m-1).

REFERENCES:
patent: 3582634 (1971-06-01), Bartlett
patent: 3761699 (1973-09-01), Sather
patent: 4013879 (1977-03-01), Bornmann et al.
patent: 4543641 (1985-09-01), Fukuta et al.
patent: 4679165 (1987-07-01), Rainer
patent: 4685077 (1987-08-01), Loo
patent: 4878191 (1989-10-01), Oguchi

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