Manufacturing method for a power MISFET

Details Manufacturing method for a power MISFET Manufacturing method for a power MISFET

1991-06-05

1992-02-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 41, 437203, 437228, 148DIG126, H01L 21335

Patent

active

050875779

ABSTRACT:
A manufacturing method for a low-voltage power MISFET which utilizes three maskes (photosteps) is provided. In the first step, a polysilicon layer is structured and a cell field and edge zones are manufactured. An oxide layer is then applied, this being opened in the second photostep above the cells and the edge zones and between the edge and the cells. A metal layer is then applied, this being interrupted between the cells and the edge zones with the third photostep. Field plates and a channel stopper are thus produced.

REFERENCES:
patent: 4055884 (1977-11-01), Jambotkar
patent: 4199774 (1980-04-01), Plummer
patent: 4613883 (1986-09-01), Tihanyi
patent: 4918026 (1990-04-01), Kosiak et al.
Japan Patent Disclosure, Nov. 12, 1986, vol. 10, No. 332, "Semiconductor Device", Tetsuo Iijima.

Affiliated with

Also associated with

Rating

Manufacturing method for a power MISFET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Manufacturing method for a power MISFET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method for a power MISFET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-781614