PLL clock synthesizer using current controlled ring oscillator

Details PLL clock synthesizer using current controlled ring oscillator PLL clock synthesizer using current controlled ring oscillator

1991-03-08

1992-08-04

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

307603, 307605, 331 25, 331 34, 331 57, H03B 502, H03K 513, H03L 7093, H03L 7099

Patent

active

051362600

ABSTRACT:
A high frequency clock signal synthesizer circuit employs a single fixed reference clock signal to generate one or more variable frequency clock signals. A phase comparator and a variable count counter generate a control signal from the reference clock and circuit output and provide it to a voltage controlled oscillator. High frequency stability of the voltage controlled oscillator is provided by a ring oscillator with a control signal response which is linear even at high frequencies. The ring oscillator employs an odd number of inverting delay stages coupled in series in a ring configuration, each delay stage having an input, an output, an inverter coupled to the input and a controllable current source buffering the switching transistors of the inverter from the output. A bias circuit controls the current of the current source and thereby controls the delay of each delay stage and thus the frequency of the ring oscillator. The buffering of the switching transistors from the output nodes of the delay stages prevents transient effects due to parasitic capacitances and process variations from affecting the current to the output node and hence from affecting the delay of the delay stage and the frequency of the ring oscillator.

REFERENCES:
patent: 4988960 (1991-01-01), Tomisawa
patent: 5036216 (1991-07-01), Hohmann et al.
"Design of PLL-Based Clock Generation Circuits", D. K. Jeong, et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.

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