Self-planarized gold interconnect layer

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357 54, G01L 2354, G01L 21283

Patent

active

049705733

ABSTRACT:
Formation of an interconnect structure having a self-planarized dielectric layer between successive layers of metallization is accomplished by conformally depositing a dielectric layer over the entire structure (including underlying regions and contact base metallization) to which the interconnect pattern is to be plated. Atop the dielectric layer a sacrificial layer is conformally deposited. Thereafter apertures are etched through both the sacrificial and dielectric layers in accordance with a prescribed interconnect plating pattern that has been photolithographically mapped onto the laminate structure. The aspect ratios of the apertures through the laminate are such that metal to be subsequently deposited therethrough is confined to the exposed surface area of the underlying topography but not on the sidewalls of the apertures through the dielectric layer. The sacrificial layers (and overlying metal plate) are then removed leaving only the patterned conformed dielectric layer and the deposited metal. The main body portion of the interconnect structure is now plated onto the deposited metal pattern to a thickness in the apertures of the dielectric which is slightly below the top surface of the dielectric layer. Thereafter, a second, thin dielectric layer is non-selectively conformally deposited over the entire structure. Contact vias for a second layer of metal to be formed over the top surface of the second dielectric layer are selectively etched through this second dielectric layer to expose surface portions of the underlying plated metal.

REFERENCES:
patent: 4398341 (1983-08-01), Geipel, Jr. et al.
patent: 4728627 (1988-03-01), Mase et al.
patent: 4771071 (1988-09-01), Tobin et al.
patent: 4851369 (1989-07-01), Ellwanger et al.

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