Quasi-accumulation mode FET

Details Quasi-accumulation mode FET Quasi-accumulation mode FET

1985-08-28

1988-01-05

Buczinski, Stephen C.

357 16, 357 64, H01L 2980, H01L 29161, H01L 29167

Patent

active

H00004111

ABSTRACT:
A Field Effect Transistor (FET) capable of withstanding increased positive gate biasing with respect to the source contact without incurring the penalty of drawing excessive gate current, comprising a semi-insulating substrate layer; an active channel layer of doped n-type semi-conductor material disposed on the substrate layer; a first heteroepitaxial semi-insulating layer of a semi-insulating material having a bandgap greater than the bandgap of the active channel layer material disposed on said active channel layer. The first heteroepitaxial layer has a top surface, a designated first region, a designated second region, and a designated middle section disposed therebetween wherein the first region and the second region of the first heteroepitaxial layer are implanted with activated donor impurities to form its source and drain regions. The device is also provided with conventional source, drain and gate contacts. In a preferred embodiment, a heavily donor doped Gallium arsenide heteroepitaxial layer is disposed between the source contact and the first heteroepitaxial layer and between the drain contact and the first heteroepitaxial layer. In one embodiment, the first heteroepitaxial layer is impurity doped with chromium or vanadium.

REFERENCES:
patent: 4297783 (1981-11-01), Casey, Jr. et al.
patent: 4424525 (1984-01-01), Mimura
patent: 4559547 (1985-12-01), Shiraki et al.
patent: 4593301 (1986-06-01), Inata et al.
patent: 4605945 (1986-08-01), Katayama et al.
patent: 4641161 (1987-02-01), Kim et al.

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