Method for fabricating integrated circuit structures with full d

Details Method for fabricating integrated circuit structures with full d Method for fabricating integrated circuit structures with full d

1975-06-30

1976-08-24

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 156 17, 357 49, 427 86, H01L 21263

Patent

active

039765113

ABSTRACT:
An integrated circuit structure with full dielectric isolation, i.e., the electrical isolation is provided by electrically insulative material, is formed by ion bombarding a silicon substrate with ions such as nitrogen, oxygen or carbon to implant subsurface region containing such ions and heating the resulted bombarded substrate to a temperature sufficient to react the introduced ions with the substrate to form a subsurface layer which has a different etchability than silicon. An epitaxial layer of monocrystalline silicon is then deposited on the substrate, after which a pattern of regions of electrically insulating material is formed extending through the epitaxial layer beyond the substrate surface into contact with the subsurface layer to laterally surround a plurality of pockets in said silicon. An electrically insulative layer is formed on the surface of the epitaxial layer continuous with the electrically insulating lateral regions. The silicon substrate below the subsurface layer is removed by etching in a solvent in which silicon is more etchable than is the subsurface layer to expose the subsurface layer, and the subsurface layer is etched away with a solvent in which this layer is more etchable than are the lateral regions of electrically insulating material. As a result, the planar surfaces of the silicon pockets are exposed, and selective conductivity-determining impurities may be introduced into the silicon pockets to form the devices of the integrated circuit.

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