Mixed size radix recoded multiplier

Details Mixed size radix recoded multiplier Mixed size radix recoded multiplier

1989-09-15

1990-10-23

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 752

Patent

active

049657623

ABSTRACT:
An array multiplier utilizing a predetermined recoding algorithm minimizes operating speed by using two different radices. Special product terms must be formed to implement the recording algorithm. In order to avoid delaying the computation of partial products until after the time special products are formed, two recoding radices may be used. Partial products can be calculated from terms formed by a smaller sized radix during the same time the special product terms are being calculated. Initial use of the smaller radix eliminates an immediate need for the special product bits which improves multiplier speed by minimizing time required to form a final product.

REFERENCES:
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4546446 (1985-10-01), Machida
patent: 4745570 (1988-05-01), Diedrich et al.
patent: 4807175 (1989-02-01), Tokumaru et al.
patent: 4864528 (1989-09-01), Nishiyama

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