Dynamic memory refresh circuit with a flexible refresh delay dyn

Details Dynamic memory refresh circuit with a flexible refresh delay dyn Dynamic memory refresh circuit with a flexible refresh delay dyn

1989-11-27

1990-10-23

Shaw, Gareth D.

Boots, shoes, and leggings

36424691, 364247, 364258, 3642581, 364244, 364270, 3642702, G06F 100

Patent

active

049657224

ABSTRACT:
A microprocessor includes an execution unit executing a program according to an instruction, an instruction prefetch circuit storing a plurality of instructions to be executed by the execution unit, a refresh control circuit controlling a refresh operation of a dynamic memory coupled to an external bus and a control unit. The control unit receives bus access request signals from the execution unit and from the instruction prefetch circuit, respectively, and a refresh request signal from the refresh control circuit and sends a refresh grant signal to the refresh control circuit in response to the refresh request signal when both the bus access request signals are absent. The refresh control circuit generates a first refresh request signal and a second refresh request signal. The control unit generates the refresh grant signal in response to the first refresh request signal only when both the bus access request signals from the execution unit and the instruction prefetch circuit are absent, but generates the refresh grant signal at any time the second refresh request signal is generated. The refresh operation is performed at least once and a counter is decremented when the refresh is granted in response to the first refresh request signal and the refresh operation is performed a plurality of times with equivalent decrementing of the counter when the refresh is granted in response to the second refresh request signal.

REFERENCES:
patent: 4535330 (1985-08-01), Carey et al.
patent: 4625301 (1986-11-01), Berger

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