Power down scheme for idle processor components

Details Power down scheme for idle processor components Power down scheme for idle processor components

1994-08-12

1997-09-09

Harvey, Jack B.

39580032, G06F 132

Patent

active

056665377

ABSTRACT:
Power down circuitry in a processor for controlling power delivered to functional units of the processor, comprising first and second power down circuits. The first power down circuit comprises a state machine having a decoded instruction as input and a control signal as output. The control signal disables a clock signal to a floating point unit (FPU) when the decoded instruction is not a floating point instruction. The second power down circuit comprises a prediction circuit that generates a predict signal when a cache access cannot occur. The predict signal disables a clock signal to a cache.

REFERENCES:
patent: 5392437 (1995-02-01), Matter et al.
patent: 5420808 (1995-05-01), Alexander et al.
patent: 5452401 (1995-09-01), Lin
patent: 5452434 (1995-09-01), MacDonald
patent: 5457790 (1995-10-01), Iwamura et al.
patent: 5481733 (1996-01-01), Douglis et al.

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