CMOS logic array layout

Details CMOS logic array layout CMOS logic array layout

1989-03-23

1990-10-23

Larkins, William D.

357 44, 357 45, H01L 27102, H01L 27105

Patent

active

049656511

ABSTRACT:
An integrated logic circuit with complementary transistors which is constructed from cells which form reproductions of logic equations, in which each cell has at least three transistors arranged one next to the other in a row and three complementary transistors arranged one next to the other. Series arrangements of transistors or transistor circuits in one row corrugated to parallel arrangements of transistors or transistor circuits in the other row. This arrangement results in compact layouts which are easy to design with computer assistance. The arrangement is particularly useful for MSI and LSI circuits.

REFERENCES:
patent: 3356858 (1967-12-01), Wanlass
patent: 3646665 (1972-03-01), Kim
patent: 3783047 (1974-01-01), Paffen et al.
RCA COSMOS Manual, RCA, Somerville, N.J., 1971, pp. 24-26.
Faggin et al, Solid State Electronics, Aug. 1970, pp. 1129-1131 and 1143.
RCA COS/MOS Datebook, #SSD 203, (RCA, Somerville, 1972), p. 83, CD4019.
Electronics, Aug. 30, 1971, pp. 38-43 (especially FIG. 6 and 7a).

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