Dual synthesizer including programmable counters which are contr

Details Dual synthesizer including programmable counters which are contr Dual synthesizer including programmable counters which are contr

1991-09-30

1992-09-01

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307271, 307529, 328155, 331 2, H03L 700, H03K 513

Patent

active

051442540

ABSTRACT:
A frequency synthesizer comprising at least two main PLL's, where each PLL has programmable dividers in both its input path (M and P) and its feedback path (N and Q), and where the first PLL is driven by a reference source of frequency F.sub.ref and has output Fl=(.sup.N /.sub.M) *F.sub.ref, and where this output serves as the input to the second main PLL, whose output in turn is F.sub.out =(.sup.Q /.sub.P) *Fl=(.sup.Q /.sub.P)*(.sup.N /.sub.M)*F.sub.ref, and each of the programmable counters is controlled by a calculation and control means, said synthesizer utilizing a method to produce an output frequency F.sub.out that is a close approximation to a requested frequency F.sub.req. The method includes doing several approximations to the ratio .sup.F req/F.sub.ref, and picking the best, calculating the four integers, generating several signals, and dividing them by said integers, locking said loops, and thereby producing F.sub.out. In one form of the invention, an approximation .sup.X 1/Y.sub.1 is made to the ratio .sup.F req/F.sub.ref and then X.sub.1 and Y.sub.1 are factored into Q.sub.1 *N.sub.1 and P.sub.1 *M.sub.1 respectively. In a preferred embodiment, an adjustable reference under control of the calculation and control means allows more than one approximation to be made, and the error for each to be determined. After a plurality of runs, each with its assigned error, one of the low error runs can be chosen, and the corresponding M.sub.1,N.sub.1, P.sub.1 and Q.sub.1 values used the program the counters. In a second form of the invention, the method uses starting values for M and N and therewith calculates approximate values for P and Q. Then, using these values for P and Q, even better approximate values for M and N are calculated, and then these four values are used to program the four counters of the two PLL's. This latter method allows severe limits to be placed on the frequency range of the intermediate PLL, thus allowing it to be a very low noise PLL.

REFERENCES:
patent: 4516084 (1985-05-01), Crowley
patent: 4673891 (1987-06-01), Remy
patent: 4785260 (1988-11-01), Paneth
patent: 4862107 (1989-08-01), Paneth

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