Latch-up verification device

Details Latch-up verification device Latch-up verification device

1993-04-27

1997-06-10

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 364491, G06F 1750

Patent

active

056382863

ABSTRACT:
A latch-up verification device including a latch-up verifying portion (3) which automatically performs a latch-up verification upon a layout pattern specified by layout pattern data (D1) by using transistor information (D4) with back gate terminal information given from the layout pattern data (D1) as a function of connection between a source terminal of respective transistors having the same back gate terminal information and a well region including the transistors, whereby the automatic latch-up verification with a constant accuracy is performed upon a layout pattern of CMOS structure with greatly increased efficiency.

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Menozzi et al., "Latch-Up Testing in CMOS IC's," IEEE J. of Solid State Physics, Aug. 90, pp. 1010-1014.
Momose et al., "Novel Test Structures for the Characterization of Latch Up Tolerance in a Bipolar and Mosfet Device," IEEE, 1991, pp. 225-230.
Takahiro Aoki, "A New Latch Up Test Structure for Practical Design Methodology for Internal Circuits in the Standard Cell-based CMOS/BiCMOS LSIs", Proc. IEEE, Mar. 1992, pp. 18-23.

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