Power-on-reset (POR) circuit having power supply rise time indep

Details Power-on-reset (POR) circuit having power supply rise time indep Power-on-reset (POR) circuit having power supply rise time indep

1990-11-26

1992-09-01

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307591, 307594, 307451, G11C 1100

Patent

active

051441594

ABSTRACT:
An output of a power-on-reset (POR) circuit is coupled to another circuit which needs to have the logic states thereof reset during each time a power supply used to power same is switched on. The POR circuit includes a first input circuit for generating an output signal that tracks the power supply output voltage Vdd approximately a first predetermined threshold below Vdd, as Vdd ramps up and further includes a second input circuit which generates an output signal which tracks approximately a second predetermined threshold above a second fixed voltage level, e.g., ground. The POR circuit further includes a comparator which compares the output signals from the first and second input circuits and switches an output signal thereof from a first to a second logic state once the input circuit output signals cross each other. A buffer is typically coupled to the output of the comparator to limit loading on same so as not to affect the comparator switching point.

REFERENCES:
patent: 3895239 (1975-07-01), Alaspa
patent: 4409501 (1983-10-01), Eickerman et al.
patent: 4572966 (1986-02-01), Hepworth
patent: 4634905 (1987-01-01), Campbell, Jr.
patent: 4698531 (1987-10-01), Jones
patent: 4788454 (1988-11-01), Tanagawa et al.
patent: 4874965 (1989-10-01), Campardo et al.
patent: 4885476 (1989-12-01), Mahabadi
patent: 4970408 (1990-11-01), Hanke et al.

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