Method and apparatus for pipe line processing with a single arit

Details Method and apparatus for pipe line processing with a single arit Method and apparatus for pipe line processing with a single arit

1983-02-02

1986-09-23

Hoffman, James R.

Boots, shoes, and leggings

G06F 930, G06F 938

Patent

active

046139354

ABSTRACT:
The invention employs an execution control unit consisting of a look up memory, three instruction registers and logic gates to control pipe line processing by an ALU. During such processing the sequential steps required to execute a program instruction are overlapped so that the ALU and its associated memory are always busy. The three instruction registers are provided to receive and retain up to three instructions which may be in process at a given time. The memory is preferably divided into a plurality of banks to improve the performance of the system by reducing the occurrence of a memory busy condition. To facilitate pipe lining an instruction format is employed having a fixed location for the data field which specifies the register to be used for address preparation.

REFERENCES:
patent: 4373180 (1982-02-01), Linde
patent: 4399507 (1983-08-01), Cosgrove et al.
patent: 4454589 (1984-06-01), Miller
patent: 4541045 (1985-09-01), Kromer
patent: 4541047 (1985-09-01), Wada et al.
The Architecture of Pipelined Computers, Peter M. Kogge, Hemisphere Publishing Corp., .COPYRGT.1981, pp. 212-244.

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