Dual field effect transistor structure for compensating effects

Details Dual field effect transistor structure for compensating effects Dual field effect transistor structure for compensating effects

1978-02-06

1979-08-28

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 22, 357 23, 357 24, G11C 1928, H01L 2978, H01L 2980

Patent

active

041662237

ABSTRACT:
A dual field effect transistor structure for reducing the effects of threshold voltage of one of the field effect transistors as reflected to a signal source device which is coupled thereto is disclosed. More specifically, a p-channel enhancement mode field effect transistor having a surface conduction channel and an n-channel depletion mode field effect transistor having a buried conduction channel are formed in a semiconductor structure such that both transistors have a common gate. A voltage potential is applied to the common gate to affect the first and second depletion regions in the semiconductor structure respectively associated with the enhancement mode and depletion mode transistors to render a quiescent threshold voltage of the enhancement mode transistor which is reflected to the measuring device. The semiconductor structure is initially electrically biased in conjunction with the voltage potential applied to the common gate to cause the first and second depletion regions to pinch off the buried conduction channel substantially eliminating current flow therethrough. The signal source device may be coupled to the source of the enhancement mode transistor to conduct a first current through the surface conduction channel. This first current screens the electric field lines which are produced by the voltage potential applied to the gate to cause a modulation of the first depletion region. This modulation effects a second current in the buried conduction channel of the depletion mode transistor. A resistor network which is coupled between the drain of the depletion mode transistor and the common gate is utilized to detect the second current and accordingly control the value of the gate voltage potential in a sense which causes the first and second depletion regions to substantially pinch off the buried conduction channel or reduce the second current being conducted therethrough. In this manner, the gate voltage potential is adjusted to substantially maintain the quiscent threshold voltage.

REFERENCES:
patent: 3283221 (1966-11-01), Heiman
patent: 3639813 (1972-02-01), Kamoshida et al.
patent: 3896483 (1975-07-01), Whelan
patent: 3918070 (1975-11-01), Shannon
patent: 4000504 (1975-05-01), Berger

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