Method and apparatus for wafer level prediction of thin oxide re

Details Method and apparatus for wafer level prediction of thin oxide re Method and apparatus for wafer level prediction of thin oxide re

1995-05-30

1997-06-10

Karlsen, Ernest F.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324769, G01R 3126

Patent

active

056380062

ABSTRACT:
An IC wafer containing thin oxide is fabricated to include at least two differentially-sized plate areas that may be upper plates of capacitors, or gates of associated MOS transistors. Before testing, the thin gate oxide underlying these plate areas is intentionally stressed by applying a stress current between these plates and the substrate. The stress current magnitude is scaled to the plate area such that each plate sees a substantially constant current density. Because weak oxide defects occur somewhat uniformly throughout the thin oxide, a larger plate or gate will overlie more weak oxide defects than will a plate or gate. If wafer test leakage current between the larger plate or gate and substrate exceeds leakage current between the smaller plate or gate and substrate, weak oxide is indicated because the defect is area dependent. By contrast, charge-induced damage is substantially independent of the areas of the plates or gates, due to the scaling of the stress-inducing currents. Thus, if test leakage current on the wafer is substantially the same for the large and small sized plates or gates, charge-damaged oxide is indicated because the damage is not area dependent. If desired, defects in the thin (gate) oxide may be identified by examining the characteristics of the test MOS devices. The gate-like plates (and if present associated MOS devices) are sufficiently small to be fabricated within scribe lines of the wafer to be tested.

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"Charge Buildup Damage to Gate Oxide", Calvin Gabriel, VLSI Technology, Inc.:Microelectronic Process, Senses, and Controls, 0-8194-1362-5/94; SPIE vol. 2091/239.
"How Plasma Etching Damages Thin Gate Oxides", Calvin T. Gabriel, VLSI Technology and James P. McVittie, Stanford University; Jun. 1992, Solid State Technology. pp. 81-87.

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