Semiconductor device having planarized wiring with good thermal

Details Semiconductor device having planarized wiring with good thermal Semiconductor device having planarized wiring with good thermal

1995-06-23

1997-06-10

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257763, 257752, 257764, 257767, H01L 2348, H01L 2352, H01L 2940

Patent

active

056379242

ABSTRACT:
A plurality of contact holes having different sizes are formed in an insulating film formed on the substrate. A first barrier metal layer is formed on the insulating film, and a tungsten layer is uniformly formed on the first barrier metal layer. The tungsten layer is etched back to form plug-shaped tungsten regions in small contact holes and sloped tungsten regions in large contact holes. The central area of the first barrier metal layer in the large contact hole is exposed. A second barrier metal layer is formed covering the plug-shaped tungsten region and the tapered tungsten region and the exposed first barrier metal layer and sandwiching the plug-shaped and sloped tungsten regions between the first and second barrier metal layers, preventing pinch-through of Al atoms from an Al layer to be thereafter formed, into the substrate, even when the first barrier metal layer is damaged during etch-back.

REFERENCES:
patent: 4876223 (1989-10-01), Yoda et al.
patent: 4926237 (1990-05-01), Sun et al.
patent: 4960732 (1990-10-01), Dixit et al.
patent: 5202579 (1993-04-01), Fujii et al.
patent: 5233217 (1993-08-01), Dixit et al.
patent: 5442235 (1995-08-01), Parrillo et al.
patent: 5466971 (1995-11-01), Higuchi
patent: 5472912 (1995-12-01), Miller

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