Digital data receiver having DC offset cancelling preamplifier a

Details Digital data receiver having DC offset cancelling preamplifier a Digital data receiver having DC offset cancelling preamplifier a

1993-07-16

1995-07-04

Chin, Stephen

Pulse or digital communications

Receivers

Automatic baseline or threshold adjustment

375345, 330259, H04L 2506, H04L 2510, H04L 2508

Patent

active

054307651

ABSTRACT:
A digital data receiver comprises a pre-amplifier for receiving a digital data input signal and a correction signal to produce a data output signal. A dc offset cancelling circuit is responsive to the data output signal for generating the correction signal to cancel dc offset contained in the digital data input signal. A post-amplifier receives the data output signal from the pre-amplifier and a reference signal. A peak detector is responsive to an output of the post-amplifier for detecting a peak amplitude thereof and generating the reference signal so that the post-amplifier has a first gain value during the time the data input signal is absent or less than its peak amplitude, and a second gain value approximately equal to twice the first gain value for a predetermined time after the peak amplitude of the data input signal is reached. The post-amplifier and peak detector have substantially equal operating characteristics.

REFERENCES:
patent: 3688205 (1972-08-01), Burger
patent: 4577155 (1986-03-01), Kobayashi et al.
patent: 4724315 (1988-02-01), Goerne
patent: 4736391 (1988-04-01), Siegel
patent: 4792998 (1988-12-01), Toussaint
patent: 5025456 (1991-06-01), Ota et al.
patent: 5119404 (1992-06-01), Aihara
patent: 5295161 (1994-03-01), Dreps et al.

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