Method of preventing latch-up failures of CMOS integrated circui

Details Method of preventing latch-up failures of CMOS integrated circui Method of preventing latch-up failures of CMOS integrated circui

1987-06-08

1989-11-07

Buczinski, Stephen C.

Fishing, trapping, and vermin destroying

437 20, H01L 21265

Patent

active

H00007072

ABSTRACT:
A method for preventing latch-up in an integrated circuit structure, and in particular, in a CMOS structure, includes the use of a high-energy blanket or maskless ion implant that reduces the substrate resistance by creating a highly ion doped buried layer in the semiconductor device. The thickness and the positioning of the heavily doped layer can be accurately ascertained through the ion implantation process. The transition region between the highly doped buried layer and the lightly doped substrate is sharper, and thus the suppression of latch-up is more effective than in prior devices fabricated with prior techniques. An increase in the holding and critical currents is found, due to the reduced substrate resistance.

REFERENCES:
patent: 3595716 (1971-07-01), Kerr et al.
patent: 3895965 (1975-07-01), MacRae et al.
patent: 4161417 (1979-07-01), Yim et al.
patent: 4224733 (1980-09-01), Spadea
patent: 4282648 (1981-08-01), Yu et al.
patent: 4317686 (1982-03-01), Anand et al.
patent: 4418469 (1983-12-01), Fujita
patent: 4454524 (1984-12-01), Spence
patent: 4536947 (1985-08-01), Bohr et al.
Hu and Bruce, IEEE Electron Device Letters, vol. EDL-5, No. 6, Jun. 1984, . 211-214 "CMOS Structure".
Takacs et al., IEDM 83, 1983 IEEE, pp. 156-163 "Comparison of Latch-up in P- and N well CMOS".
Jerdonek, et al., IEDM 82, 1982 IEEE, pp. 450-453 "Reduced Geometry CMOS Technology".
Huang et al., IEDM 82, 1982, IEEE, pp. 454-457 "Characterization of CMOS Latch up".
Byrne, P. F. "Megavolt Arsenic Implantation into Si", Electronic Research Laboratory, Aug. 12, 1982, pp. 1-13.
Byrne et al, "Megavolt Ion Implantation into Silicon".
Byrne et al, "Damage Induced Through Megavolt Arsenic Implantation" Appl. Phys. Lett., 41(6) Sep. 15, 1982, pp. 537-539.
Sadana et al, "Recrystallization . . . ", Appl. Phys. Lett. 44 (3) Feb. 1, 1982, pp. 301-303.
Washburn et al, "Crystalline to Amorphous . . . ", Nuclear Instruments & Methods, pp. 345-350.
Byrne et al, "Megavolt Arsenic Implantation", Thin Solid Films, 95 (1982) pp. 363-367.
Byrne et al, "Megavolt Boron & Arsenic Implantation", Materials Research Society, Symposia Proceeding.
Byrne, P. F. "Megavolt Dopant Implantation" Presentation for Degree of Doctor of Philosophy.
Byrne, P. F. "High Energy Ion Implantation" J. Appl. Physics 54 (2), Feb. 1983, pp. 1146-1147.

Affiliated with

Also associated with

Rating

Method of preventing latch-up failures of CMOS integrated circui does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of preventing latch-up failures of CMOS integrated circui, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of preventing latch-up failures of CMOS integrated circui will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-76356