Method of manufacturing a DRAM capacitor

Semiconductor device manufacturing: process – Making passive device – Stacked capacitor

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438253, H01L 2120

Patent

active

059727705

ABSTRACT:
A DRAM capacitor and a method of making the same includes the provisions of providing a semiconductor substrate having a MOS transistor with a gate and source/drain regions formed thereabove. A first insulating layer covers the semiconductor substrate. A conducting plug is formed in the first insulating layer. Thereafter, a multi-layered structure is formed above the first insulating layer and the conducting plug, with at least one pair of alternately formed layers, including a first conducting layer followed by a second insulating layer. Then, an opening is formed through the multi-layered structure to expose the conducting plug. Subsequently, a pattern is etch-defined on the multi-layered structure to expose part of the first insulating layer. After that, part of the second insulating layer is etched away, to shape the multi-layered structure into a cross-sectional profile similar to two towers, each in the form of a vertical stack of Ts, with each tower standing side-by-side and adjacent to each other. Next, a lower electrode layer is formed over the surfaces of the multi-layered structure as well as the exposed surface of the conducting plug. A dielectric layer is formed over the lower electrode layer. An upper electrode layer is formed over the dielectric layer.

REFERENCES:
patent: 5834357 (1998-11-01), Kang
patent: 5879987 (1999-03-01), Wang
patent: 5903024 (1999-05-01), Hsu

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