Fishing – trapping – and vermin destroying
Patent
1994-07-18
1995-07-04
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 52, 257316, H01L 21266, H01L 218247
Patent
active
054299705
ABSTRACT:
A new method of obtaining an improved coupling ratio and short channel effect in a Flash EEPROM memory cell is shown. A trench is etched into a semiconductor substrate. A thick gate oxide layer is formed over the surface of the substrate and within the trench. A layer of silicon nitride is deposited and anisotropically etched away to leave spacers on the sidewalls of the trench. The spacers are overetched to expose an upper portion of the gate oxide layer on the trench sidewalls. The gate oxide layer not covered by the spacers is removed, exposing the horizontal silicon surface of the substrate in the bottom of the trench and the upper portion of the silicon sidewalls of the trench above the spacers. A tunnel oxide layer is grown on the exposed silicon surfaces of the substrate and within the trench wherein the controllable small area of tunnel oxide within the trench provides an improved coupling ratio and the long channel afforded by the trenched channel region improves the short channel effect of the memory cell. The silicon nitride spacers are removed. A first polysilicon layer is deposited within the trench. An interpoly dielectric layer is deposited over the first polysilicon layer followed by a second polysilicon layer. The layers are patterned to form a stacked polysilicon structure wherein the first polysilicon layer forms a floating gate and the second polysilicon layer forms a control gate. Source and drain regions are formed on either side of the stacked polysilicon structure.
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Booth Richard A.
Chaudhuri Olik
Saile George O.
United Microelectronics Corporation
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