Method and apparatus for processing an error flag of a PCM signa

Details Method and apparatus for processing an error flag of a PCM signa Method and apparatus for processing an error flag of a PCM signa

1985-10-04

1987-04-21

Smith, Jerry

Excavating

371 39, G06F 1110

Patent

active

046602003

ABSTRACT:
Method and apparatus for reproducing a PCM signal are disclosed. The PCM signal comprises a plurality of word-interleaved frames. Each frame comprises a plurality of data blocks and a parity block. Each data block comprises a plurality of words, each word comprises an upper symbol and a lower symbol arranged symbol by symbol. A plurality of upper symbols included in different blocks and a plurality of lower symbols included in the same word form a parity code generated from the symbols in the respective symbol sequences and a plurality of error detection/correction blocks. In the error flag processing of the PCM signal, the input PCM signal is reproduced, errors are detected and corrected based on the corresponding parity codes for a plurality of upper symbol error detection/correction sequences and a plurality of lower symbol error detection/correction sequences, error flags indicating the number of errors detected and the number of errors corrected are generated for the error detection/correction sequences based on the result of the error detection/correction, a flag indicating a maximum significant value is detected from two flags generated for the upper and lower symbol error detection/correction sequence of the same word and selecting that flag as a common flag to both sequences.

REFERENCES:
patent: 4437185 (1984-03-01), Sako
patent: 4577319 (1986-03-01), Takeuchi
patent: 4593394 (1986-06-01), Tomimitsu
patent: 4593395 (1986-06-01), Immink

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