CMIS Level shift circuit

Details CMIS Level shift circuit CMIS Level shift circuit

1982-11-24

1985-03-19

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307270, 307279, 307475, 307585, H03K 502, H03K 1716, H03K 3353, H03K 1710

Patent

active

045061645

ABSTRACT:
A semiconductor device includes a first circuit (C1, C1') driven by a first power supply (V.sub.cc) and a second circuit (C2) driven by a second power supply (V.sub.pp) which has a higher potential than the first power supply. A P-channel transistor (Q.sub.18) is provided on the input side of the second circuit and is controlled by the feedback of an output of the second circuit. The P-channel transistor has a source connected to the second power supply. In addition, two N-channel transistors (Q.sub.19, Q.sub.20) are connected in series between the output of the first circuit and the input of the second circuit. Each of the N-channel transistors has a gate, connected to the first power supply and the second power supply, respectively.

REFERENCES:
patent: 3916430 (1975-10-01), Heuner et al.
patent: 4080539 (1978-03-01), Stewart
patent: 4216390 (1980-08-01), Stewart
patent: 4239994 (1980-12-01), Stewart
patent: 4317110 (1982-02-01), Hsu
patent: 4463273 (1984-07-01), Dingwall

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