Electrical circuit test apparatus and method

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371 49, G01R 3128, G06F 1100

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active

043588476

ABSTRACT:
An electrical circuit test apparatus and method are disclosed for detecting faults in n-input combinational circuitry. The testing is performed by the verification of the Walsh coefficients. This is an alternative to the usual Boolean based techniques. To implement the Walsh coefficient verification, a reversible counter is utilized in conjunction with a driving counter, a parity indicating means, and minor control circuitry. The output signal from the unit under test is compared with the parity signal derived from the driving counter, and where there is correspondence, the reversible counter is actuated in one direction. Where they are dissimilar, the reversible counter counts in the opposite direction. A circuit is considered faulty where the final indication in the reversible counter is zero.
It has been found that the Walsh spectrum of any given combination logic function f(x) of n independent variables x.sub.1 to x.sub.n consists of a series of 2.sup.n integer numbers, the magnitude and sign of which constitute the spectral coefficient values of f(x). Therefore, because the spectral coefficient values define the output function uniquely, the values for a network with an output fault will differ from these without fault.

REFERENCES:
patent: 3582633 (1971-06-01), Webb
patent: 3761695 (1973-09-01), Eichelberger
patent: 3924181 (1975-12-01), Alderson
patent: 4161276 (1979-07-01), Sacher et al.
S. C. Seth, Data Compression Techniques in Logic Testing: An Extension of Transition Counts, Journal Design Automation and Fault Tolerant Computing, vol. 1, No. 2, Feb. 1977, pp. 99-114.

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