Method of manufacturing small geometry MOS field-effect transist

Details Method of manufacturing small geometry MOS field-effect transist Method of manufacturing small geometry MOS field-effect transist

1993-06-18

1995-01-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437242, 437941, H01L 21265

Patent

active

053825330

ABSTRACT:
A process for suppressing hot electrons in sub half micron MOS devices wherein a gate oxide and a gate electrode are formed on the surface of a silicon substrate and source and drain regions are ion implanted into the silicon substrate using the gate electrode as a mask. The process includes forming a layer of silicon dioxide over the gate electrode and over the source and drain regions of the substrate, and then introducing a barrier layer forming element into the layer of silicon dioxide to form a thin barrier region to hot electrons at the interface between the silicon substrate and the silicon dioxide. In a preferred embodiment of the invention, nitrogen is introduced into the silicon dioxide by heating the wafer in a rapid thermal processor and in the presence of a nitrogen containing gas at an elevated temperature for a predetermined time. The nitrogen containing gas may be selected from the group consisting of nitrogen trifluoride, ammonia and nitrous oxide. In an alternative embodiment of the invention, fluorine atoms are introduced into the silicon substrate either as the sole barrier layer forming element (silicon fluoride) or prior to the formation of the thin silicon nitride region. The fluorine atoms form good strong silicon-fluorine bonds in the silicon substrate and thereby further enhance the hot electron suppression. In a third embodiment, nitrogen and fluorine are reacted in a rapid thermal processor to form a composite barrier layer of Si.sub.3 N.sub.4 and SF.

REFERENCES:
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patent: 5098866 (1992-03-01), Clark et al.
patent: 5237188 (1993-08-01), Iwai et al.
patent: 5258333 (1993-11-01), Shappir et al.
patent: 5264380 (1993-11-01), Pfiester

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