Method and apparatus for detecting errors in a system that emplo

Details Method and apparatus for detecting errors in a system that emplo Method and apparatus for detecting errors in a system that emplo

1995-02-24

1997-09-09

Baker, Stephen M.

Excavating

G06F 1110

Patent

active

056663714

ABSTRACT:
An apparatus for and method of detecting errors in a system which employs multi-bit wide memory elements. The error correction code (ECC) of the present invention is odd weighted and thus has an odd number of check bits. Further, the exemplary ECC has a single code in each of the check bit columns. The error correction code of the present invention may detect byte errors thereby providing a mechanism for detecting errors within system which employs multiple bit wide memory elements. The data word in an exemplary embodiment may comprise 44 bits including 36 data bits, one IF bit, and seven check bits. The 44 bit data word may comprise eleven (11) four bit bytes wherein each of the eleven (11) four bit bytes of the 44 bit data word are stored in a different memory element. Each of the 44 bits of the data word are stored in an appropriate one of the eleven (11) memory elements to maximize the error detection capability of the exemplary error correction code. The exemplary ECC may: detect and correct all single bit errors in the 44 bit data word; detect all two bit errors in the 44 bit data word; detect all three bit errors in each of the eleven (11) four bit bytes of the 44 bit data word; and detect all four bit errors in each of the eleven (11) four bit bytes of the 44 bit data word.

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