Clock signal reproducing network for PCM signal reception

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

328 63, 328120, 331 49, H03K 378

Patent

active

040041620

ABSTRACT:
A clock signal reproducing network for PCM signal reception is capable of reproducing a clock signal even if the clock component is absent in the input digital signal for a prolonged period of time. The network includes a clock signal component extracting circuit and a bandpass filter for extracting and band-limiting the clock signal component in a received digital signal. An envelope detection circuit and a level decision circuit are connected to receive the output of the bandpass filter to provide a control signal to an output switching circuit. When the amplitude of the envelope of the filter output is high, the output of the bandpass filter is used directly as a reproduced clock signal. When the amplitude of the envelope is low, the clock signal obtained immediately before the filter amplitude becomes small is derived repeatedly from a delay circuit as a substituted clock signal.

REFERENCES:
patent: 3289097 (1966-11-01), Martin
patent: 3350580 (1967-10-01), Harrison
patent: 3593044 (1971-07-01), McNeilly
patent: 3671776 (1972-06-01), Houston
patent: 3790892 (1974-02-01), Tan et al.

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