Pipeline processor with prefetch circuit

Details Pipeline processor with prefetch circuit Pipeline processor with prefetch circuit

1990-11-07

1992-09-15

Eng, David Y.

Boots, shoes, and leggings

3642631, 3642617, 3649382, G06F 930, G06F 940, G06F 938

Patent

active

051485320

ABSTRACT:
In a pipeline processing microprocessor, an instruction fetch unit is keyed to the formation or nonformation of a conditional branch micro-instruction result to determine the subsequent macro-instruction to be fetched from an external memory or cache. A macro-instruction is first decoded in an instruction decoder to generate micro-addresses which address is a micro-ROM. The first micro-instruction retrieved from the micro-ROM contains information for executing a conditional discrimination, a signal requesting branch ready, and a subsequent micro-address for the actual execution of the branch request in accordance with the result of the conditional discrimination. When the branch condition is satisfied, a micro-address generating circuit feeds the subsequent micro-instruction to a micro-ROM address decoder and the least significant bit of the subsequent micro-address to a micro-address analyzing circuit. The branch ready information of the first micro-instruction is also fed to the micro-address analyzing circuit to prefetch a target branch macro-instruction from an associated memory before the micro-ROM outputs the micro-instruction, corresponding to the subsequent micro-address, to the instruction execution unit, in effect bypassing the delay associated with micro-ROM decoding.

REFERENCES:
patent: 4003033 (1977-01-01), O'Keefe et al.
patent: 4179737 (1979-12-01), Kim
patent: 4187539 (1980-02-01), Eaton
patent: 4399507 (1983-08-01), Cosgrove et al.
patent: 4551798 (1985-11-01), Horvath
patent: 4777594 (1988-10-01), Jones et al.

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