Scalable neural array processor and method

Details Scalable neural array processor and method Scalable neural array processor and method

1991-08-05

1992-09-15

MacDonald, Allen R.

G06F 1518

Patent

active

051485150

ABSTRACT:
An Array Processor and Method for a Scalable Array Neural Processor (SNAP) permits computing as a dynamic and highly parallel computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. The Scalable Neural Array Processor (SNAP) uses a unique intercommunication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP's packaging and expansion capabilities are addressed, demonstrating SNAP's scalability to larger networks. The array processor is scalable. It has an array of function elements and a plurality of orthogonal horizontal and vertical processing elements for communication, computation and reduction. This structure permits in a first computation state the generation of a set of output values and in the first communication state the processing elements produce, responsive to the output values, first reduction values. In a second computation state processing elements, responsive to the first reduction values, generate vertical output values, and in a second computation state the vertical output values are communicated back to the inputs of the function elements. Responsive to a third computation state responsive to the vertical output values, a second set of output values is generated by said function elements, and in a third communication state the horizontal processing elements produce second reduction values. In a fourth computation state the horizontal processing elements generate horizontal output values, and responsive to a fourth communication state the horizontal processing elements communicate the horizontal output values back to the inputs of the function elements.

REFERENCES:
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An Enhanced Parallel Toroidal Lattice Architecture for Large Scale Neural Networks; Fujimoto et al.; IJCNN 18-22 Jun. 1989.
"Parallel Distributed Processing vol. 1; Foundations" Cambridge, Mass.: MIT Press 1986, pp. 45-76, 319-362. D. E. Rumelhart, J. L. McClelland and the PDP Research Group.
"Neurons with Graded Response have Collective Computational Properties like those of Two-State Neurons" J. J. Hopfield Proceedings of the Nat'l Acad. of Sci 81, pp. 3088-3092, May 1984.

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