Adder-subtracter for signed absolute values

Details Adder-subtracter for signed absolute values Adder-subtracter for signed absolute values

1990-06-05

1992-09-15

Mai, Tan V.

Boots, shoes, and leggings

364787, 36471501, G06F 750

Patent

active

051483866

ABSTRACT:
An adder-subtracter for signed absolute values wherein two inputs of signed absolute values are operated with circuits based on the two's complement representation and the operated on result is output in the form of signed absolute value. The adder-subtracter executes two kinds of a subtractive operations for inputs in the form of signed absolute values in parallel. One of the operated results should then be selected according to the sign of the subtracted result, and inverted to be output depending on the sign so as to obtain a subtractive result directly in the form of a signed absolute value.

REFERENCES:
patent: 3814925 (1974-06-01), Spannapel
patent: 4811272 (1989-03-01), Wolrich et al.
patent: 4849921 (1989-07-01), Yasumoto
patent: 4908788 (1990-03-01), Fujiyama et al.
patent: 4953115 (1990-08-01), Kanoh
patent: 4979141 (1990-12-01), Gelinas et al.

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