Process for fabricating a stacked capacitor

Details Process for fabricating a stacked capacitor Process for fabricating a stacked capacitor

1994-04-22

1995-07-25

Thomas, Tom

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 218242

Patent

active

054361869

ABSTRACT:
A method for fabricating a capacitors having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming an interdigitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.

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"3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", IEDM, 1988, pp. 593-595, by T. Ema et al.

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