Method of making semiconductor device including MOS type field e

Details Method of making semiconductor device including MOS type field e Method of making semiconductor device including MOS type field e

1994-01-26

1995-07-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 27, 437 41, 437 43, 437 44, 437149, 437186, 437913, 257327, 257336, H01L 21265

Patent

active

054361788

ABSTRACT:
A semiconductor device includes an MOS field effect transistor having a structure in which the tops of its source/drain regions are covered with a polycrystalline silicon layer. The impurity concentration distribution in its depth direction of the source/drain regions of the MOS field effect transistor is such that the concentration is sufficiently high in an area necessary to have conductivity a prescribed depth away from the surface of the semiconductor substrate, and the impurity concentration drastically decreases in areas deeper than that. Thus, a punch through phenomenon in positions relatively deep in the channel region is suppressed, and an MOS field effect transistor having its channel length reduced to 0.5 .mu.m and less and achieving high performance can be obtained. Such an MOS field effect transistor can be produced by implanting an impurity a number of times, controlling appropriately the peak value and the peak position of the impurity concentration, before and after or only after the formation of the polycrystalline silicon layer.

REFERENCES:
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patent: 4992389 (1991-02-01), Ogura et al.
patent: 5024959 (1991-06-01), Pfiester
patent: 5141891 (1992-08-01), Arima et al.
patent: 5177571 (1993-01-01), Satoh et al.
"Computer Analysis of Punch-Through in MOSFETs", N. Kotani and S. Kawazu, Solid-State Electronics, vol. 22, No. 1-E, 1979, pp. 63-70.

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