Method and apparatus for designing an integrated circuit

Details Method and apparatus for designing an integrated circuit Method and apparatus for designing an integrated circuit

1995-04-21

1997-09-09

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364491, G06F 1750

Patent

active

056662882

ABSTRACT:
A method and apparatus for designing and manufacturing integrated circuits (ICs) involves providing an initial library of IC cells (106) and a behavioral circuit model (100) in order to create a gate schematic netlist (102). The gate schematic netlist (102) is optimized by changing individual transistor sizes, power rail sizes, cell pitch, and the like in a step (103). Once the optimization has occurred, the initial library can no longer be used to place and route the IC. Therefore, a hybrid logic cell library is created from the gate schematic netlist (102) via a step (105). This hybrid library and the above optimizations provides a placed and routed IC via a step (126) in a short design cycle while optimizing performance of the IC.

REFERENCES:
patent: 4613940 (1986-09-01), Shenton et al.
patent: 4813013 (1989-03-01), Dunn
patent: 5084824 (1992-01-01), Lam et al.
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5274568 (1993-12-01), Blinne et al.
patent: 5406497 (1995-04-01), Altheimer et al.
patent: 5452227 (1995-09-01), Kelsey et al.
patent: 5459673 (1995-10-01), Carmean et al.
patent: 5487018 (1996-01-01), Loos et al.
patent: 5493508 (1996-02-01), Dangelo et al.
patent: 5510998 (1996-04-01), Woodruff et al.
patent: 5519627 (1996-05-01), Mahmood et al.
patent: 5572436 (1996-11-01), Dangelo et al.
patent: 5572437 (1996-11-01), Rostoker et al.
S. Sapattnekar, V. Rao and P. Vaidya, "A Convex Optimization Approach to Transistor Sizing for CMOS Circuits," ICCAD-91, Nov. 11-14, 1991, Santa Clara, CA pp. 482-485.
D. Hill, D. Shugard, A. Dunlop, J. Fishburn, "A Set of Switch-Level Synthesis Tools," 1990 IEEE Intl. Symposium on Circuits and Sytems, vol. 4., pp. 2571-2575.
A. Dunlop, J. Fishburn, D. Hill, D. Shugard, "Experiments Using Automatic Physical Design Techniques for Optimizing Circuit Performance," Intl. Symp. on Circuits & Systems, 1990, pp. 847-851.
Dwight Hill, "SC2D: A Broad-Spectrum Automatic Layout System," IEEE 1987 Custom Integrated Circuits Conference, May 4-7. pp. 729-732.
J. Shyu, J. Fishburn, A. Dunlop, A. Santiovanni-Vincentelli, "Optimization-Based Transistor Sizing," IEEE 1987 Custom Integrated Circuits Conference, May 4-7, pp. 417-420.
J. Fishburn,, A Dunlop, "TILOS: A Posynomial Programming Approach to Transistor Sizing," IEEE Intl. Conference on Computer Aided-Diesign, 1985, pp. 328-328.
N. Maheshwari, S. Sapatnekar, "Gate Size Optimization for Row-based Layouts," 38th Midwest Symposium on Circuits and Systems, vol. 2, pp. 777-779, 1996.
Lee et al., "A Graphic Interface for Power System Simulation," 1993 Power Industry Computer Application Conference, pp. 269-276.
Ramachandran et al., "SYMCELL-A Symbolic Standard Cell System," IEEE Journal of Solid-State Circuits, vol. 23, No. 3, Mar. 1991, pp. 449-452.

Affiliated with

Also associated with

Rating

Method and apparatus for designing an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for designing an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for designing an integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-73814