Implementation of the IEEE 1149.1 boundary-scan architecture

Details Implementation of the IEEE 1149.1 boundary-scan architecture Implementation of the IEEE 1149.1 boundary-scan architecture

1992-04-10

1994-01-25

Levy, Stuart S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 307465, 328206, H03K 3289, H03K 312

Patent

active

052818640

ABSTRACT:
A circuit for a boundary-scan cell for the JTAG Architecture, the circuit including a capture section(50) coupled in cascade to an update section(52),
and each section comprising a flip-flop (34,36)having a clock input for receiving a common clock signal (TCK, TCKB) and a multiplexer having a first input for receiving an input data signal, a second input coupled to an output of the flip-flop, an output coupled to a flip-flop input, and a select input for receiving a control signal for selectively coupling the first or second input to the multiplexer output.

REFERENCES:
patent: 4628216 (1986-12-01), Mazumder
patent: 4926451 (1990-05-01), Yoshihara et al.
patent: 4970410 (1990-11-01), Matsushita et al.
patent: 5083049 (1992-01-01), Kagey
patent: 5124573 (1992-06-01), Wong
patent: 5128970 (1992-07-01), Murphy
patent: 5173626 (1992-12-01), Kudou et al.

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