Method for manufacturing a solid electrolytic capacitor array

Details Method for manufacturing a solid electrolytic capacitor array Method for manufacturing a solid electrolytic capacitor array

1998-10-20

2000-03-21

Bowers, Charles

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438399, H01L 2120

Patent

active

060402296

ABSTRACT:
A solid electrolytic capacitor array includes a substrate (12) made of conductive silicon, and an insulation film (15) which is formed with a plurality of contact holes is formed on an upper surface of the substrate. A plurality of contact layers (18) which are respectively connected to the substrate through the contact holes is formed on the insulation film. A plurality of chips each of which is a sintered unit of tantalum powder are arranged on the contact layers, respectively. A plurality of solid electrolytic layers which are respectively electrically insulated from the tantalum powder of the chips by insulation films are provided on the chips, respectively. A covering resin layer (25) covers the chips in a manner that portions of the solid electrolytic layers of the chips are respectively exposed, and cathode electrodes are formed on the covering resin layer so as to be electrically conducted to the solid electrolytic layers being exposed from the covering resin layer. An anode electrode (28) are formed on a lower surface of the substrate so as to be electrically conducted to the tantalum powder of the respective chips via the substrate and the contact layers.

REFERENCES:
patent: 4097916 (1978-06-01), Piper
patent: 4616290 (1986-10-01), Watanabe et al.
patent: 4853827 (1989-08-01), Hernandez

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