Dynamic MOS RAM

Details Dynamic MOS RAM Dynamic MOS RAM

1976-03-12

1977-07-26

Canney, Vincent P.

Communications: electrical

Digital comparator systems

G11C 1104

Patent

active

040386465

ABSTRACT:
An improved dynamic MOS RAM employing capacitive storage memory cells having a single active device per cell. The RAM includes several improved circuits and techniques which reduce power consumption and pattern sensitivity and which also provide a higher speed memory. Complementary input/output lines are employed which are coupled to alternate pair of the bit-sense lines making the use of a bistable output latch and push-pull output buffer more advantageous. The sense amplifiers associated with each of the bit lines are activated by a dual sloped signal to reduce noise and increase sensitivity and gain in the amplifiers. The output lines of the address buffers are initially "high" and then brought to their final level after an address is received by the buffers.

REFERENCES:
patent: 3922647 (1975-11-01), Broeker, Jr.
patent: 3959781 (1976-05-01), Mehtz et al.
patent: 4004285 (1977-01-01), Bormann et al.

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